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LOW POWER ADDER DESIGN for VLSI

By Manish Jain

LOW POWER ADDER DESIGN for VLSI

By Manish Jain

0 - Default Title
Description
This wok proposes an energy efficient approximate adder that provides low power high performance addition without severe quality degradation. The proposed adder introduces area efficient approximate logic that is used to adder least significant bits of the adder. The effectiveness of the adder is analyzed over the well known accurate and approximate adders by implementing on Tanner and MATLAB. The simulation result shows that proposed adder outperform over the existing adder and can be effectively applied to the applications that can tolerate small amount of error.
Product details
Binding:
Paperback
Number of Pages:
52
Release Date:
2025-06-27
Publication Date:
2025-06-27
Publisher:
Scholars' Press
Languages:
Original: English
ISBN10:
6208847796
ISBN13:
9786208847791
GPSR Manufacturer Reference:
[email protected]
Weight:
96 g
Height:
150 cm
Width:
220 cm
Thickness:
4 cm
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