HIGH RESOLUTION AND LOW JITTER FULL CUSTOM ADPLL ARCHITECTURES

Name: HIGH RESOLUTION AND LOW JITTER FULL CUSTOM ADPLL ARCHITECTURES
Brand: LAP LAMBERT Academic Publishing
Availability: OutOfStock
Rating: 5 (1 reviews)

By Jahangir, Mohd Ziauddin

0 - Default Title

Description

All digital PLLs are being considered as an effective replacement due to high immunity of digital circuits to PVT variations. However, ADPLLs suffer from the problem of low resolution and high jitter/ phase noise apart from fundamental problems of complex design procedures. It was found through literature surveys and experimental verifications that there are still some challenges related to resolution, jitter/phase noise that need to be addressed, in the existing ADPLLs. Similarly, it was also found that there is a shortcoming in the models used to describe ADPLLs. In this regard, an extensive classification of existing ADPLL architectures was made. Some of the architectures found in literature were critically examined by redesigning and simulation verification at various levels of design with a wide set of simulation/emulation tools. Comparative analysis was done and shortcomings in each architecture were critically identified. Methods to improve resolution and phase noise were proposed and verified using simulation.

Product details

Binding:

Paperback

Number of Pages:

216

Release Date:

2025-05-19

Publication Date:

2025-05-19

Publisher:

LAP LAMBERT Academic Publishing

Languages:

Original: English

ISBN10:

6208445582

ISBN13:

9786208445584

Weight:

340 g

Height:

150 cm

Width:

220 cm

Thickness:

13 cm

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