Optimizing Assertion Sets Using Logic Synthesis Techniques
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Optimizing Assertion Sets Using Logic Synthesis Techniques
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Description
The result looked at first as unexpected, however, an attentive reflection reveals that in a formal verification setting, adding more dependencies to an assertion reduces the number of states that the formal verification tool needs to explore in order to prove whether the assertion is true or false. This also explains why the merged Karnaugh maps did exceptionally well while the heuristics test did poorly in comparison. In a formal setting, merging Karnaugh maps allowed IFV to prove the assertion set 4 times faster than the initial non-optimized set of non-redundant assertions.
Product details
- Type:
- Book
- Binding:
- Paperback
- Languages:
-
Original:
English
- Number of Pages:
-
120
- Publisher:
-
LAP LAMBERT Academic Publishing
- Publication Date:
-
2013-12-13
- ISBN / EAN:
-
9783659498879
- Weight:
-
197 g
- Dimensions:
-
15/22/1 cm
- GPSR Manufacturer Reference:
-
[email protected]
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