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A Fully Integrated Phase Locked Loop at 61.44 GHz for High-Speed Wireless LANs

By Atheer Barghouthi

A Fully Integrated Phase Locked Loop at 61.44 GHz for High-Speed Wireless LANs

0 - Default Title
Description
In this dissertation, a fully integrated 61.44 GHz PLL was designed and measured. Capacitor multiplication was used to enable the integration of the loop filter on chip and the effect of the capacitor multiplier on the total PLL phase noise performance was quantified and evaluated. Additionally, the effect of the HBT transistor parasitics on the negative resistance of Colpitts oscillators was analyzed and the negative resistance equation, which is available in literature, was extended. Furthermore, a design methodology for choosing the load impedance of Colpitts oscillators was explained. Moreover, the frequency limits of the operation of HBT cross coupled oscillators at high frequencies were studied and an extended expression of the negative conductance of the oscillator and an expression for the frequency at which the conductance of the oscillator changes its value from negative to positive, were derived.
Product details
Binding:
Paperback
Edition:
1
Number of Pages:
128
Release Date:
2013-03-01
Publication Date:
2013-03-01
Publisher:
TUDpress
Languages:
Published: English, Original: English
ISBN10:
3944331044
GPSR Manufacturer Reference:
[email protected]
Height:
21 cm
Width:
14.8 cm
Thickness:
0.9 cm
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