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Cost-effective Methods for High-speed Nanometer CMOS VLSI Design

By Charbel Akl

Cost-effective Methods for High-speed Nanometer CMOS VLSI Design

By Charbel Akl

- Default Title
Description
The semiconductor industry has been following Moore's law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.
Product details
Binding:
Paperback
Number of Pages:
132
Release Date:
2025-08-25
Publication Date:
2025-08-25
Publisher:
LAP LAMBERT Academic Publishing
Languages:
Original: English
ISBN10:
6208480620
ISBN13:
9786208480622
GPSR Manufacturer Reference:
[email protected]
Weight:
215 g
Height:
150 cm
Width:
220 cm
Thickness:
8 cm
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