Leakage Optimization Techniques
% SALE
Leakage Optimization Techniques
% SALE
% SALE
Description
Rise in use of battery operated applications gives leakage power dissipation importance over the area and speed considerations.Many portable devices, has energy constraints for longer battery lifetime. Though the subthreshold shows potential toward satisfying the ultra-low-power requirements of portable systems, it holds design issues at device level and circuit level both for Analog IC design. These issues lead to significant increase in the design complexity of integrated circuits. Very few applications addresses these challenges for subthreshold circuit design in an integrated and comprehensive manner. There are many methods for determining the least leakage input vector. In, This book provides a detailed analysis of concerns related to IC performance. For design time technique, Dual threshold CMOS is used; where, transistors with low threshold voltage (Vth) are used in critical paths and high Vth transistors for non-critical paths. Another approach is to use (MTCMOS) in which high threshold voltage transistors are place This book also presents a qualitative summary of the work reported in the literature by various researchers in the design of digital subthreshold circuit.
Product details
- Type:
- Book
- Binding:
- Paperback
- Languages:
-
Original:
English
- Number of Pages:
-
96
- Publisher:
-
LAP LAMBERT Academic Publishing
- Publication Date:
-
2020-03-13
- ISBN / EAN:
-
9786200786647
- Weight:
-
161 g
- Dimensions:
-
15/22/1 cm
Die gelieferte Auflage kann ggf. abweichen.
Currently sold out
Back in stock email
Add to Wishlist
